Working Principle of L6599d (l6599d Pin Function and Application Circuit)

L6599d is packaged in double row 16 pin so and dip. It is a dual channel adjustable Synchronous Step-Down Switching power supply controller, which can output high and low switching signal voltages to drive two FET tubes. The working voltage is 8.85 16V, the working temperature is - 40 150 ℃, and the power consumption is 0.83w. Control chip suitable for half bridge series resonant soft switching converter. On the basis of the previous generation product l6598d, a variety of functions are added, such as special output directly connected to power factor corrector (PFC), two-stage overcurrent protection (OCP), self-locking prohibition input, light load burst mode operation and a power on / power off sequence or undervoltage protection input.

characteristic

1.50% duty cycle, frequency conversion control, resonant half bridge

2. High precision oscillator

3. Reach 500KHz working frequency

4. Two levels of OCP: frequency shift and latch off

5. The interface has PFC controller

6. Disable input latch

7. Burst mode works under light load

8. The input has switching sequence or undervoltage protection

9. Nonlinear soft start is monotonic output voltage rise

The 10.600v compatible high side gate driver integrates bootstrap diode and high DV / dt immunity

11. - 300 / 800mA high side and low side grid drives have UVLO pull-down

2. L6599d pin diagram

3. L6599d pin function

1. CSS: soft start end. This pin has an indirect capacitance CSS with the ground (GND) and a resistance RSS with the 4 pin (rfmin) to determine the maximum operating frequency during soft start. When VCC (12 pin) UVLO (low voltage lockout), line (7 pin) 1.25V or 6V, dis (8 pin) 1.85v (Forbidden end), isen (6 PIN) 1.5V, delay (2 pin) 3.5V, and when the voltage of isen exceeds 0.8V or exceeds 0.75V for a long time, the chip closes and capacitor CSS discharges through the internal switch of the chip to make the restart process soft start.

2. Delay: overload current delay shutdown terminal. One resistor RD and one capacitor CD are connected in parallel to the ground at this end to set the maximum duration of overload current. When the voltage of isen pin exceeds 0.8V, the chip will charge CD through a 150ua constant current source. When the charging voltage exceeds 2.0V, the chip output will be turned off and the power on the soft start capacitor CSS will be discharged. After the circuit is turned off, the overcurrent signal disappears, the 3.5V power supply for CD charging inside the chip is turned off, and the power on CD is discharged through Rd. when the voltage is lower than 0.3V, the soft start starts. In this way, in the overload or short circuit state, the chip works in the intermittent working state again and again. (RD shall not be less than 2V / 150ua ＝ 13.3K Ω. The greater the RD, the shorter the allowable overcurrent time and the longer the shutdown time.)

3. CF: timing capacitor. A capacitor CF is connected to the ground, and the 4-pin rfmin to the ground is matched with the switching frequency of the programmable oscillator.

4. Rfmin: minimum oscillation frequency setting. Pin 4 provides 2V reference voltage, and a resistor rfmin is connected from pin 4 to the ground to set the minimum oscillation frequency. A resistor rfmax is connected from pin 4 and grounded through the optocoupler controlled by the feedback loop, which will be used to adjust the oscillation frequency of the exchanger. Rfmax is the maximum operating frequency setting resistance. The RC network between pin 4-pin 1-gnd realizes soft start.

5. STBY: standby, intermittent working mode threshold (1.25V) The 5-pin is controlled by the feedback voltage. Compared with the internal 1.25V reference voltage, if the 5-pin voltage is lower than the 1.25V reference voltage, the chip is in a static state and has only a small static working current. When the 5-pin voltage exceeds the reference voltage of 50mV, the chip starts working again. In this process, soft start does not work. When the load drops below a certain level (light load) This function enables the chip to implement intermittent operation mode through rfmax and optocoupler (see the structure diagram). If there is no circuit association between pin 5 and pin 4, the intermittent operation mode will not be enabled.

6. Isen: input terminal of current detection signal. Pin 6 detects the current in the main circuit through resistance shunt or capacitive current sensor. This input terminal is not intended to realize cycle by cycle control, so the average current information must be obtained through filtering. When the voltage exceeds the 0.8V threshold (there is a 50mV return difference, that is, once it exceeds 0.8V, it still works as long as it does not fall below 0.75V) , the soft start capacitor of pin 1 is discharged inside the chip, and the working frequency is increased to limit the power output. In the case of short circuit of the main circuit, this usually makes the peak current of the circuit almost constant. Considering that the overcurrent time is set by pin 2, if the current continues to increase, although the frequency increases, when the voltage exceeds the reference voltage (1.5V) of another comparator The driver will shut down and the energy loss will almost return to the level before startup. The detection information is locked. The chip will be restarted only when the power supply voltage Vcc is lower than UVLO. If this function is not used, please ground pin 4.

7. Line: input voltage detection. This terminal is protected by the AC or DC input voltage sampled by the voltage divider (between the system and PFC). When the detection voltage is lower than 1.25V, the output is closed (not locked) And release the soft start capacitor. When the voltage is higher than 1.25V, restart the soft start. This comparator has hysteresis effect: if the detection voltage is lower than 1.25V, the internal 15ua constant current source is turned on. A capacitor is indirectly connected to the ground at pin 7 to eliminate noise interference. The voltage of this pin is limited by the internal 6.3V zener diode, and the conduction of 6.3V zener diode turns off the output of the chip (non locking) . if this function is not used, the pin voltage is between 1.25V and 6V.

8. Dis: disable, the locking drive is turned off. A comparator is internally connected to this pin. When the voltage of this pin exceeds 1.85v, the chip will be turned off in a locking manner. The chip can start working again only when the chip working voltage Vcc is reduced below the UVLO threshold. If this function is not used, please ground this pin.

9. Pfc_stop: open the control channel of PFC (power factor correction) controller. This pin is opened to stop the operation of PFC controller for protection purpose or intermittent operation mode. When the chip is controlled by DIS "1.85v, isen" 1.5V, line "6V and STBY When 1.25V is closed, the output of pin 9 is pulled down. When the voltage at delay terminal exceeds 2V and does not return to below 0.3V, this terminal is also pulled down. During UVLO (low voltage lockout), this pin is open. This pin is allowed to be suspended and not used.

10. GND: chip ground. The loop current is the sum of the low-end gate drive current and the chip bias working current. All relevant grounds should be connected to this pin and separated from the pulse control loop.

11. LVG: low-end gate drive output. This pin can provide a small drive current of 0.3A. The source is 0.8A (?). The suction (?) peak current drives the low-end MOS transistor of the half bridge circuit. During UVLO, LVG is pulled down to the ground level.

12. VCC: the power supply includes the signal part of the chip and the gate drive of the low-end MOS transistor. Connecting a small filter capacitor (0.1uF) is conducive to the chip signal circuit to obtain a clean bias voltage.

13. N.C.: empty pin, used for high voltage isolation and increasing the spacing between VCC and pin 14. This pin is not connected internally, isolated from high voltage, and can meet the requirements of safety regulations (leakage distance) on PCB.

14. Out: floating ground of high-end gate drive. Provide current return circuit for high-end gate drive current. It shall be carefully arranged to avoid too large burr below the ground.

15. HvG: high end floating gate drive output. This pin can provide a small drive current of 0.3A. The source is 0.8A (?). The suction (?) peak current drives the upper MOS tube of the half bridge circuit. A resistor is internally connected to pin 14 (out) through the chip to ensure no floating drive during UVLO.

16. Vboot: high-end gate drive floating power supply. A bootstrap capacitor CBOOT is connected between pin 16 (vboot) and pin 14 (out), which is synchronously driven by a bootstrap diode inside the chip and the low-end gate driver. This patented structure replaces the commonly used external diode.

4. L6599d internal block diagram

Limit parameters

Note: the antistatic capacity (ESD) of pins 14, 15 and 16 is guaranteed to be above 900v.

5. L6599d application circuit

Application circuit (I)

Operate under no-load or very light load

When the resonant half bridge is lightly loaded or all loads are unloaded, its switching frequency is at the maximum. In order to keep the output voltage under control and avoid soft switching failure, there must be a necessary residual magnetization current flowing through the transformer. However, this current will cause a very low no-load loss when the converter is under no-load.

The drive can use 5 pins (STBY) Working in pulse intermittent working mode: if the voltage of pin 5 is lower than 1.25V, the IC enters an idle state, the two gate drives are low, the oscillator is stopped, and the soft switching capacitor CSS retains its charging state. Only the 2V voltage reference power consumption on rfmin pin and the self discharge on VCC capacitor. When the voltage of pin 5 exceeds 1.25v50mv, the IC returns to normal operation.

To realize the pulse intermittent operation mode, the voltage of STBY pin must be related to the feedback loop. The figure shows the simplest scheme, which can be matched with a narrow input voltage range.

Figure   Realize pulse intermittent working mode: narrow input voltage range

However, the switching frequency of the resonant converter also depends on the input voltage; if the input voltage range is large, the value of poutb will change greatly for the above figure. At this time, it is recommended to use the circuit in the following figure to introduce the input voltage signal to the STBY pin. Due to the strong nonlinear relationship between the switching frequency and the input voltage, experience has verified that RA / (RA RB) The correction of reduces the change of poutb to the minimum. Please carefully select that the total value of RA RB is greater than RC to minimize the effect on the voltage of line pin.

Figure   Realize pulse intermittent working mode: wide input voltage range

Application circuit (II)

LLC half bridge circuit of l6599d