Samsung and MediaTek 7 Nm 5g Smartphone Chips

This year's conference covered a series of in-depth topics, including PLL, low-power circuit, memory, SerDes, DSP and processor design. In the processor part, there are leading suppliers, as well as projects from research institutions and academia. The meeting covered intensive chip design details. The highlights of interesting details in the processor link are introduced below.

Samsung and MediaTek 7 nm 5g smartphone chips

The SoC Designs of these two 5g smartphones are from MediaTek and Samsung respectively. They focus on the CPU design of mixing different arm cores for large companies. In addition, the problem of detecting the internal voltage drop of the processing unit during heavy load is also solved.

The first demonstration came from Samsung, which chose to build a set of three cluster CPU cores. Samsung uses the arm licensed kernel in two of the three clusters, but the kernel with the best performance is designed by Samsung under the arm architecture license - Dual M4 kernel. The dual M4 core has a separate 3MB L3 cache, and the core goal is to achieve the performance level of Intel i5.

For the medium power / performance range, Samsung uses the arm cortex-a75 core. The "small" energy-saving core is the ancient cortex-a55. The power / performance gap between Samsung M4 core and cortex-a55 core is too large. Cortex-a75 core is added to make up for this gap. Samsung also added a neural processing unit to 1024 MAC computers, but did not provide much details.

Voltage drop in high-performance processors may be a problem. If too many protective belts are added to maintain a high supply voltage, more energy will be consumed. At a more energy-saving rated voltage, when a specific power consuming unit is under load - such as a GPU running high-resolution games - the internal resistance decreases, resulting in the internal voltage below the normal value. SOC suppliers build dedicated circuits to detect these voltage drops and take action to alleviate the problem. Their method is to extend the clock and reduce the circuit speed and power consumption by effectively reducing the clock speed. Samsung adopts a ring oscillation circuit, which can change the speed according to the voltage. Voltage drop detection sets a flag in the clock management unit (CMU) and halves the clock speed.

MediaTek adopts different ways to select CPU core and adheres to arm's big. Little scheme, which MediaTek calls double gear design. MediaTek uses the newer cortex-a77 CPU core to achieve strong performance. MediaTek also pointed out that the cortex-a55 small core did not keep up with the development of the performance core. Instead of adding a core with medium performance, they tried to expand the voltage range of a77 to a lower speed. Samsung has only two performance cores, and MediaTek has four a77 cores. Four a77 and four A55 cores share a 2MB L3 cache.

MediaTek's initial response to voltage drop is to provide stored charge on die, which can provide some instantaneous current, but this requires valuable die area. Therefore, it decided to stretch the clock to save die space.

A major change of MediaTek is the use of frequency locked loop (FLL) instead of phase locked loop (PLL). The FLL design has a dual clock, but this design contains uncertainty because it allows the oscillator to vary with voltage. With FLL circuit, MediaTek Vmin has been improved by about 35mV, saving 10% power consumption. MediaTek has also built a novel JTAG solution for the chip, which has a gateway tap for hierarchical access to the test circuit.

MediaTek chip also supports wifi6 and 5g independent and non independent modes. The a77 core supports a clock speed of up to 2.6 GHz. The chip has an arm Mali G-77 nine core GPU.