Important Parameters for Analog-to-digital Converter (ADC): Digital Data Output Type

Each digital output type in ADC has its own advantages and disadvantages, which should be carefully considered by designers according to specific applications. These factors depend on the sampling rate and resolution of the ADC, the output data rate, the power requirements of the system design, and other factors.

This paper will discuss the electrical specifications of each output type and its specific characteristics suitable for specific applications. We will compare these different types of outputs in terms of physical implementation, efficiency and the most suitable for each type of application.

CMOS digital output driver

CMOS is a common digital output in ADC with sampling rate less than 200 MSPs (MS / sec). A typical CMOS driver consists of two transistors (one NMOS and one PMOS) connected between the power supply (VDD) and ground, as shown in Figure 1a. This structure will cause output inversion. Therefore, the back-to-back structure shown in Fig. 1b can be used as an alternative to avoid output inversion.

When the output is low impedance, the input of CMOS output driver is high impedance. At the input of the driver, the gate impedance of the two CMOS transistors is very high because the gate is isolated from the conductive material through the gate oxide layer. The input impedance range can reach K? To m? Level.

At the driver output, the impedance is controlled by the leakage current ID, which is usually small. At this time, the impedance is usually less than several hundred?. The level swing of CMOS is about between Vdd and ground, so it may be large, depending on the VDD amplitude.

Figure 1: typical CMOS digital output driver

Due to the high input impedance and low output impedance, one of the advantages of CMOS is that one output can usually drive multiple CMOS inputs.

Another advantage of CMOS is low quiescent current. The only case where a large current occurs is when switching occurs on the CMOS driver. Whether the driver is at low level (pull to ground) or high level (pull to VDD), the current in the driver is very small. However, when the driver switches from low level to high level or from high level to low level, a low impedance path will temporarily appear between Vdd and ground. This transient current is the main reason why other technologies are used in the output driver when the converter speed exceeds 200MSPS.

Another reason is that each bit of the converter requires a CMOS driver. If the converter has 14 bits, 14 CMOS output drivers are required to transmit each bit. Generally, more than one converter is placed in a single specified package, usually eight.

When CMOS technology is adopted, it means that up to 112 output pins are required for data output. From the packaging point of view, this is unlikely to be achieved, but also produces high power consumption and makes the circuit board layout more complex. In order to solve these problems, we introduce the interface using LVDS.

LVDS digital output driver

Compared with CMOS technology, LVDS has some obvious advantages. It can operate under low voltage signal (about 350mV) and is differential rather than single ended. Low voltage swing has fast switching time and can reduce EMI problems.

This characteristic of difference can bring the benefit of common mode suppression. This means that the noise coupled to the signal is common mode to both signal paths, and most of it can be eliminated by the differential receiver.

The impedance in LVDS must be more strictly controlled. In LVDS, the load impedance should be about 100?, This is usually achieved by a parallel termination resistor on the LVDS receiver. In addition, LVDS signals shall be transmitted by controlled impedance transmission lines. The differential impedance is maintained at 100? The required single ended impedance is 50?. Figure 2 shows a typical LVDS output driver.

Figure 2: typical LVDS output driver

As shown in the LVDS output driver topology in Figure 2, the circuit operation will generate a fixed DC load current at the output power supply. This avoids current spikes in typical CMOS output drivers when the output logic state transitions. The nominal pull current / fill current in the circuit is set to 3.5ma so that the termination resistance is 100? The typical output voltage swing is 350mV. The common mode level of the circuit is usually set to 1.2V, which is compatible with 3.3V, 2.5V and 1.8V supply voltages.

There are two written standards that can be used to define LVDS interfaces. One of the most commonly used standards is ANSI / TIA / eia-644 specification, entitled "electrical characteristics of low voltage differential signaling (LVDS) interface circuits". The other is IEEE standard 1596.3, entitled IEEE standard for low voltage differential signals of scalable conformance interface (SCI).

LVDS needs to pay more attention to the physical layout of signal routing, but it can provide many advantages for the converter when the sampling rate reaches 200MSPS or higher. The constant current of LVDS enables many outputs to be driven without a large amount of current absorption required by CMOS.

In addition, LVDS can operate in double data rate (DDR) mode, in which two data bits can be output through the same LVDS driver. Compared with CMOS, the number of pins can be reduced by half.

At the same time, it also reduces the power consumption of the same amount of data output. For converter data output, LVDS does have many advantages over CMOS, but it also has some limitations like CMOS. With the increase of converter resolution, the amount of data output required by LVDS interface will become more difficult to manage for PCB layout. Moreover, the sampling rate of the converter will eventually make the data rate required by the interface exceed the capacity of LVDS.