Detailed Analysis and Advantages of Control Plane and Data Plane Video Based on FPGA

One of the biggest challenges faced by Embedded designers is to define the performance requirements of the system. The information needed to determine actual performance requirements is either unavailable or difficult to obtain. The most accurate estimates sometimes fail due to unpredictable calculated loads. The analysis usually points out that the cost-effectiveness of embedded processing system is too low for data processing requirements. Therefore, system designers are highly eager to have a scalable architecture that can adapt to potential changes in performance requirements and perform high-performance data processing. The control plane / data plane processing architecture implemented in FPGA can effectively meet the above requirements. What is control plane / data plane processing? Why might your next generation of embedded systems need it? In a system that cannot complete all processing work with software, designers can obtain other performance in many ways. They can use multiprocessors with symmetric or asymmetric processing configurations; Using hardware coprocessor; Or split the data processing task into one or more dedicated processing units - just like processing in the control plane / data plane. In this programming mode, data processing is divided into two different planes. The control plane represents algorithmic elements that have little impact on performance, such as administrative tasks, user interfaces, and operating system functions. At the same time, the data plane represents the flow of data in the system, such as video stream or audio stream and its processing. On the data plane, designers use technologies such as pipeline to enhance data throughput. Typical applications of control plane / data plane processing include streaming video, network packet processing and high-speed signal processing. Let's take a closer look at a control plane / data plane application involving real-time processing of streaming data. We will face the recognition of unique patterns of HD video streams. The implementation requires the mixed use of high-performance data processing and a typical representative of a variety of applications including the control functions of embedded microprocessors. The pixel frequency of 720p / 60Hz HD video stream is 74.25mhz. This requires a processing rate of 222.75mb per second. Assuming that a 2.5GHz dual core dual instruction processor is used to process the data, the optimal instruction rate is 10g instructions per second. Such a processor can execute 22.4 instructions for each byte of processed data. This is sufficient for some applications, but the 22.4 instructions show that the data that can be processed is very limited. Complex video processing functions, such as kernel convolution, noise reduction and other filtering functions, require higher instruction execution efficiency. The solution in this paper is to create parallel or pipelined processing units on the data plane. HD video processing is a common practical application that can divide the problem into control plane and data plane for efficient processing. As a highly parallel processing unit, FPGA is responsible for video processing in this example, and the medium performance processor inside FPGA is responsible for video processing pipeline. The processor can be dedicated to a single application or run an operating system such as Linux. The resulting hardware software hybrid implementation scheme can deliver the processing to the part that can perform the best processing, so as to realize a low-cost and high-performance data processing solution. Figure 1 shows a typical control plane / data plane system.

Figure 1: typical control plane / data plane processing system. In addition to the expensive ASIC, FPGA is the implementation method of stream data processing unit with the highest performance and the most economic benefit. Because of its flexible architecture, FPGA allows designers to implement processing systems including parallel and pipelined units. In this way, the designer can optimize the performance and delay of the system. The designer can then apply the data plane solution to an external discrete microprocessor for control. Adding the processor inside the FPGA can bring many advantages. The internal processor can greatly reduce the control delay between the processor and the data plane unit. The reduction of delay can release many processor cycles. The external processor must maintain communication with the data plane. The communication channel can be 32 bits or more, and more wires are required for addressing and control at the same time. Additional wires may require more powerful processor and FPGA packaging, resulting in increased system cost. Using PCI Express (PCIe) can greatly reduce the number of pins. Unfortunately, not all processors and FPGAs support this relatively new interface, and even if they do, the cost of PCIe devices is much higher than that of similar devices without PCIe. The implementation of control plane processor and data plane in FPGA can reduce the number of devices, board space and power consumption, and finally form a low-cost solution. There are both hard core processors such as PowerPC and soft core processors such as Xilinx MicroBlaze in FPGA. FPGA based processors can be configured according to application requirements. The system based on FPGA can transplant decision-making and computing functions between processor and FPGA logic, so as to realize system level optimization. Implementation of control plane / data plane system some tools can simplify the implementation of FPGA based control plane / data plane system. Compiling systems using wizards or by adjusting existing reference designs are two common methods. Through the wizard, FPGA tools can quickly assemble microprocessor systems. Using drop-down lists or check boxes, you can easily specify the target parts and the required processors and peripherals. At the same time, a signal processing pipeline with a processor bus interface can be quickly compiled for control using a tool such as MATLAB software. In addition, the c-to-hdl tool can also be used to build a digital signal pipeline. The connection of control plane / data plane can be simply completed through matching bus interface. Figure 2 shows the instruction window for starting the wizard and the final system built with the wizard.

Figure 3: clownfish detector control plane / data plane system. C-to-fpga compiler can enable developers to use new development tool sets and new technologies to solve software / hardware development problems. Developers can code the algorithm in the software first. Experience tells us that developing algorithms in software is more efficient than developing algorithms in hardware. The specific reasons are as follows: firstly, C language can enable programmers to develop algorithms at the level of high-level software language, which can not be achieved by using Verilog or VHDL hardware description language; Secondly, compared with similar hardware development tools, the debugging and testing tools for C language run faster, more efficient and generally easier to use. Equivalent to hardware algorithm, C language algorithm can run at full speed on the target processor, and the hardware algorithm needs to be tested and debugged on the simulation program first; Finally, the cost of C language development tools is much lower than that of similar hardware development tools. Therefore, engineers tend to develop algorithms in C language or similar high-level languages. Once a software language such as C language is used to verify an algorithm, the designer must measure its performance and determine whether the algorithm can run completely on the embedded processor or hardware, or whether the hardware software hybrid coprocessing implementation scheme is the best choice. Performance analysis tools can be used in this judgment process. If the code must be transferred to hardware, the designer must convert the algorithm manually or use the c-to-fpga tool. The c-to-fpga tool allows developers to quickly convert algorithms into HDL code, optimize the generated hardware processor, and execute hypothetical scenarios to balance performance and FPGA resources. The tool also enables software engineers to use the high-performance data processing logic inside FPGA, so as to become hardware engineers. Using Linux to connect the processor to the FPGA, Linux vendors working with FPGA manufacturers have developed drivers that allow the processor to communicate with and control the FPGA. First, you must configure Linux for this I / O device. The configuration step consists of two steps. First, load the customized driver into the Linux kernel: then, register the driver to a specific device number (such as 253):

The communication is completed by turning on the I / O device and then reading and writing the device. The example code segment is as follows:

The advantage of FPGA, the data bandwidth requirement of signal processor system often exceeds the level that general-purpose processor can economically obtain. In this case, designers usually divide their data processing system into two processing functions: using general-purpose processor for control processing, and using hardware accelerators such as FPGA for data processing. This constitutes a control plane / data plane processing system. FPGA is very suitable for implementing control plane and data plane functions at the same time. An FPGA can contain one or more soft processors such as MicroBlaze and / or hard processors such as PowerPC. Integrating them into FPGA can realize low delay and high bandwidth communication between control plane processor and data plane processing system. With the help of wizard and pre built reference design, the system compilation for embedded and data processing functions is simple and clear. By transforming the algorithm prototype built in C language into high-performance hardware processing unit, c-to-fpga tool helps to optimize this process. Finally, the communication and control coding between the processor and FPGA signal processing pipeline can be easily completed by using the available linux driver. Our case study is a typical application example. In this example, it is impractical to process HD video stream by low-cost general-purpose processor, but it can be easily solved by signal processing pipeline inside FPGA. The processor is then released to provide user interface, network and system management functions, and monitor and control the signal processing pipeline at the same time.