Design of Flash Paging Secondary Boot Program Based on DM642

0 Introduction

    TMS320DM642 is a high-performance digital multimedia processor introduced by TI company. It has two-level memory, high-speed buffer and ultra long instruction word structure. Its advantages of fast operation speed, small volume and low power consumption make it widely used in the field of multimedia processing. The application system based on flash boot DM642 is developed. After the system is powered on, the automatic boot mechanism of the system automatically loads the application program in flash into the on-chip RAM to run. However, due to the automatic boot mechanism, only 1 KB code in off chip flah can be loaded into RAM. This requires the development of a boot program that can load all applications, that is, a secondary boot program.

1. Boot mode of DM642

    DM642 has three main boot modes:

    (1) Do not load. The CPU directly starts executing the instructions in the memory at address 0. If the memory here is SDRAM, the CPU will hang first until SDRAM initialization is completed.

    (2) ROM loading. The 1 KB program located in the ROM of the external CE1 space is first moved to address 0 through DMA / EDMA. Although the loading process starts only after the chip is released from the reset signal, when the chip is still in reset, it begins to prepare for the above transmission. After the transmission is completed, the CPU exits the reset state and starts executing the instruction at address 0. The program storage format in ROM shall be consistent with the endpoint mode of the chip.

    (3) Host load. The core CPU stays in the reset state, and the rest of the chip remains normal. The external host initializes the storage space of the CPU through the host interface, including the on-chip configuration register. After all initialization work is completed, write "1" to dspint of interface control register to end boot. After the CPU exits the reset state, the instruction is executed from address 0.

    In the application system based on DM642, the boot mode of ROM loading is mainly adopted, and the application program is stored in flash through external flash chip. The application program still exists after the system is powered off, so that the system can run offline. Moreover, with the help of secondary boot program, the development of large-scale application based on DM642 will be more convenient and flexible.

2. Connection between DM642 and flash

    In this paper, the tms320dm642agdk of TI company is used for DM642, and the am29lv033c of AMD company is used for flash.

    The working clock of TMS320DM642 can reach 720 MHz and the processing performance can reach 5760 MIPs. It accesses the off chip memory through the external memory interface (EMIF). The EMIF interface is divided into four spaces, namely ce0 Ce3. Flash is mapped to CE1 space, and 8-bit ROM loading mode is adopted when power on. Am29lv033c is a 4 M & times; 8 B, 3 V single supply nonvolatile memory.

    CE1 subspace is configured as an 8-bit asynchronous static memory interface connected to flash. Since there are only 20 external address buses of DM642, the maximum addressing range of CE1 is 1m & times; 8 b。 CE1 only allocates the first half of the addressing space to flash and the second half to other resources, that is, the maximum addressable range is 512k × 8 b。 In order to address all the space of flash, the flash can be paged and managed. The flash is divided into 8 pages, and the page selection is controlled by the page address register located in CPLD through PA19, PA20 and PA21. The connection diagram between DM642 and flash is shown in Figure 1.

Paging technology is used to address all flash spaces, and each page of flash is mapped to the same address space of CE1 (0x9000000 0x9007ffff). During the boot process of the secondary boot program, whenever the flash current page reaches the end of the page, change the output level of PA19, PA20 and PA21 through the page address control register to activate the next page and complete the boot process. In this paper, taking the video acquisition, coding and transmission program based on DM642 as an example, the design process of the secondary boot program of DM642 is described in detail.

3 secondary boot program

3.1 guidance process

    The secondary boot loader is placed at the starting address of flash. Once the DSP is powered on and reset, the secondary boot loader will be loaded to address 0 of ram through the automatic loading mechanism of DM642. At this time, the CPU will reset and start to execute the secondary boot loader. The boot process of the secondary boot program is as follows: first, configure the EMIF register, including global control register, CEX space control register, SDRAM control register, timing control register and extended control register. Then, obtain the program entry address, and then obtain the number of bytes and target address of each block according to the format of data block, and start copying the code. When the number of bytes obtained is 0, the boot ends and the CPU jumps to C_ Int00, establish the C language running environment, and execute from main (). The boot process is shown in Figure 2.

3.2 secondary boot program design

    According to the boot process of the secondary boot program, the implementation code of the secondary boot program is written, and the secondary boot program is written in assembly language. The following is the specific implementation of each part.

    (1) Configure the EMIF register. Define the base address of EMIF register EMIF base = 0x01800000, and define the configuration value of each register as:

(2) Copy the application code. Define the address of the boot table as copy_ Table = 0x90000400, the implementation code is as follows:

(3) The code that determines whether to reach the end of the page. The address of the page address control register is 0x90080011. During code copying, always judge whether the loading pointer points to the beginning of the next page. If yes, return to 0x9000400. If not, continue copying. The implementation code is as follows:

(4) Perform a jump. After the code copy is completed, the boot ends and the jump instruction is executed. The code is as follows:

In addition, corresponding command files must be written to cooperate with the boot program to complete the boot process. In this example, put the secondary boot program in the. Boat load section and add the following code to the command file:

4 experimental results

    Add the assembly file of the secondary boot program into the actual project, and apply for the corresponding memory space for the secondary boot program in the command file, compile and connect to generate an executable file (. Out). Then, the executable file is converted into CCS loadable data file through hex6x conversion tool.

    Establish the connection between CCS simulation environment and DM642 development board, and burn the data file into flash through CCS simulation platform. After burning, disconnect the development board from CCS, and the power on test program can run normally.

5 Conclusion

    This paper introduces the design method of the secondary boot program of flash paging boot of DM642, and gives some implementation codes. Practice shows that this method is feasible. This provides a way for the practical application development based on DM642.